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IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER, DUAL 3-STATE OUTPUTS AND BUS-HOLD
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * VCC = 2.5V 0.2V * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * Available in SSOP, TSSOP, and TVSOP packages
IDT74ALVCH16903
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
* High Output Drivers: 24mA * Suitable for heavy loads
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM(2) VTERM(3) TSTG IOUT IIK IOK ICC ISS Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND (Outputs Only) Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND -0.5 to +4.6 -0.5 to VCC+0.5 -65 to +150 -50 to +50 50 -50 100
Unit V V C mA mA mA mA
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. This value is limited to 4.6V maximum.
This 12-bit universal bus driver is built using advanced dual metal CMOS technology. This device has dual outputs and can operate as a buffer or an edge-triggered register. In both modes, parity is checked on APAR, which arrives one cycle after the data to which it applies. The YERR output, which is produced one cycle after APAR, is open drain. MODE selects one of the two data paths. When MODE is low, the device operates as an edge-triggered register. On the positive transition of the clock (CLK) input and when the clock-enable (CLKEN) input is low, data setup at the A inputs is stored in the internal registers. On the positive transition of CLK and when CLKEN is high, only data setup at the 9A-12A inputs is stored in their internal registers. When MODE is high, the device operates as a buffer and data at the A inputs passes directly to the outputs. The 11A/YERREN serves a dual purpose; it acts as a normal data bit and also enables YERR data to be clocked into the YERR output register. When used as a single device, parity output enable (PAROE) must be tied high; when parity input/output (PARI/O) is low, even parity is selected and when PARI/O is high, odd parity is selected. When used in pairs and PAROE is low, the parity sum is output on PARI/O for cascading to the second ALVCH16903. When used in pairs and PAROE is high, PARI/O accepts a partial parity sum from the first ALVCH16903. A buffered output-enable (OE) input can be used to place the 24 outputs and YERR in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. The ALVCH16903 has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH16903 has "bus-hold" which retains the inputs' last state whenever the input bus goes to a high-impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.
APPLICATIONS:
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT COUT Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
* 3.3V high speed systems * 3.3V and lower voltage computing systems
NOTE: 1. As applicable to the device type.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
(c)1999 Integrated Device Technology, Inc.
SEPTEMBER 1999
DSC-4911/1
IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
1 33 56 12 (1A-11A/YERREN, APAR) 1A-12A, APAR 13 (1A-8A) 8 13 13 12 (11A/YERR EN) D Q APAR 11 5 Flip Flop 10 (1A-10A) Parity Check D D Q XOR Q APAR D Q 12 (1A-12A) 12 1Y2-12Y2 1Y1-12Y1
OE M OD E CLK
13
29 CLKEN 5 (9A-12A, APAR)
Flip Flop
36 YER R
30 PARI/O
PAR OE
28
FUNCTION TABLE(1)
Inputs OE L L L L L L H MODE L L L L H H X CLKEN L L H H X X X CLK X X X A H L H L H L X Outputs 1Yx-8Yx H L Y(2) Y(2) H L Z 9Yx-12Yx H L H L H L Z
PARITY FUNCTION TABLE(1)
Inputs OE L L L L L L L L H L PAROE(2) H H H H H H H H X X 11A/ YERREN(3) L L L L L L L L X H L L L L H H H H X X PARI/O OF INPUTS APAR 1A-10A= H 0, 2, 4, 6, 8, 10 1, 3, 5, 7, 9 0, 2, 4, 6, 8, 10 1, 3, 5, 7, 9 0, 2, 4, 6, 8, 10 1, 3, 5, 7, 9 0, 2, 4, 6, 8, 10 1, 3, 5, 7, 9 X X L L H H L L H H X X H L L H L H H L H H Output YERR
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = LOW-to-HIGH Transition 2. Output level before the indicated steady-state conditions were established.
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care 2. When used as a single device, PAROE must be tied HIGH. 3. Valid after appropriate number of clock pulses have set internal register.
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IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE 1Y1 1Y2 GND 2Y1 2Y2 VCC 3Y1 3Y2 4Y1 GND 4Y2 5Y1 5Y2 6Y1 6Y2 7Y1 GND 7Y2 8Y1 8Y2 VCC 9Y1 9Y2 GND 10Y1 10Y2 PAROE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CLK 1A 11A/YERREN GND 11Y1 11Y2 VCC 2A 3A 4A GND 12A 12Y1 12Y2 5A 6A 7A GND APAR 8A YERR VCC 9A MODE GND 10A PARI/O CLKEN
PARI/O FUNCTION TABLE(1)
Inputs PAROE L L L L H OF INPUTS 1A-10A = H 0, 2, 4, 6, 8,10 1, 3, 5, 7, 9 0, 2, 4, 6, 8, 10 1, 3, 5, 7, 9 X APAR L L H H X Output PARI/O L H H L Z
NOTE: 1. This table applies to the first device of a cascaded pair of ALVCH16903 devices.
PIN DESCRIPTION
Pin Names 1A-12A 1Y1-12Y2 CLK CLKEN MODE YERREN PAROE PARI/O YERR OE APAR I/O I O I I I I I I/O O I I Data Inputs(1) 3-State Data Outputs Clock Input Clock Enable Input (Active LOW) Select Pin Error Signal Output Enable (Active LOW) Parity Output Enable (Active LOW) Parity Input/Output Error Signal (Open Drain) Output Enable Input (Active LOW) Parity Input Description
NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
SSOP/ TSSOP/ TVSOP TOP VIEW
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IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL IOH IOZ(2) VIK VH ICCL ICCH ICCZ ICC Ci Co Cio Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) YERR Output High Impedance Output Current Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current Quiescent Power Supply Current Variation Control Inputs Data Inputs YERR Output Data Outputs PARI/O VCC = 3.3V VO = VCC or GND VCC = 3.3V VO = VCC or GND VCC = 0V to 3.6V VCC = 3.6V VCC = 2.3V, IIN = - 18mA VCC = 3.3V VCC = 3.6V, VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 3.3V VI = VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND VO = VCC VO = VCC or GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- -- -- - 0.7 100 0.1 -- 5.5 5.5 5 6 7 Max. -- -- 0.7 0.8 5 5 10 10 10 10 - 1.2 -- 40 750 -- -- -- -- -- pF pF A A A A V mV A A pF A V Unit V
NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. For I/O ports, the parameter IOZ includes the input leakage current.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current VCC = 3V VCC = 2.3V VCC = 3.6V
Test Conditions VI = 2V VI = 0.8V VI = 1.7V VI = 0.7V VI = 0 to 3.6V
Min. - 75 75 - 45 45 --
Typ.(2) -- -- -- -- --
Max. -- -- -- -- 500
Unit A A A
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IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
OUTPUT DRIVE CHARACTERISTICS, xYx PORTS
Symbol Parameter VCC = 2.3V to 3.6V VCC = 2.3V VOH Output HIGH Voltage VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VCC = 2.3V to 3.6V VCC = 2.3V VOL Output LOW Voltage VCC = 2.7V VCC = 3V VCC = 2.3V IOH High-Level Output Current VCC = 2.7V VCC = 3V VCC = 2.3V VCC = 2.7V IOL Low-Level Output Current VCC = 3V PARI/O Y Port YERR Output PARI/O Y Port Y Port IOH = - 24mA, VIH = 2V IOL = 0.1mA IOL = 6mA, VIL = 0.7V IOL = 12mA, VIL = 0.7V IOL = 12mA, VIL = 0.8V IOL = 24mA, VIL = 0.8V Y Port Test Conditions(1) IOH = - 0.1mA IOH = - 6mA, VIH = 1.7V IOH = - 12mA, VIH = 1.7V IOH = - 12mA, VIH = 2V Min. VCC - 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 -12 -12 -12 -24 12 12 12 24 24 mA mA V V Unit
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
OUTPUT DRIVE CHARACTERISTICS FOR YERR AND PARI/O
Symbol VOH VOL VOL Parameter PARI/O PARI/O YERR Output only VCC = 3V VCC = 3V VCC = 3V Test Conditions(1) IOH IOL IOL
= = =
Min. - 12mA, VIH = 2V 12mA, VIL = 0.8V 24mA 2 -- --
Max. -- 0.55 0.5
Unit V V V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
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IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS FOR BUFFER MODE, TA = 25C
VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 57.5 15 VCC = 3.3V 0.3V Typical 65 17.5 Unit pF
OPERATING CHARACTERISTICS FOR REGISTER MODE, TA = 25C
VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 57 16.5 VCC = 3.3V 0.3V Typical 87.5 34 Unit pF
SIMULTANEOUS SWITCHING CHARACTERISTICS(1)
Parameter From (Input) tPLH tPHL
NOTE: 1. All outputs switching.
To (Output) Y
VCC = 2.5V 0.2V Min. 1.8 1.4 Max. 6.5 5.9
VCC = 2.7V Min. Max. 6.1 5.1
VCC = 3.3V 0.3V Min. 1.8 1.7 Max. 5 4.5 Unit ns
Register mode
CLK
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IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V 0.2V Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tSU tSU tSU tSU tSU tSU tSU tH tH tH tH tH tH tH tH tW tSK(O) Parameter Propagation Delay, Buffer Mode xAx to xYx Propagation Delay, Both Modes CLK to YERR Propagation Delay, Both Modes CLK to PARI/O Propagation Delay, Both Modes CLK to PARI/O Propagation Delay, Both Modes Mode to xYx Propagation Delay, Register Mode CLK to xYx Propagation Delay, Both Modes OE to YERR Propagation Delay, Both Modes OE to YERR Output Enable Time, Both Modes OE to xYx Output Enable Time, Both Modes PAROE to PARI/O Output Disable Time, Both Modes OE to xYx Output Disable Time, Both Modes PAROE to PARI/O Set-up Time, Register Mode, 1A-12A before CLK Set-up Time, Buffer Mode, 1A to 10A before CLK Set-up Time, Register Mode, APAR before CLK Set-up Time, Buffer Mode, APAR before CLK Set-up Time, Both Modes, PARI/O before CLK Set-up Time, Buffer Mode, 11A/YERREN before CLK Set-up Time, Register Mode, CLKEN before CLK Hold Time, Register Mode, 1A-12A after CLK Hold Time, Buffer Mode, 1A-10A after CLK Hold Time, Register Mode, APAR after CLK Hold Time, Buffer Mode, APAR after CLK Hold Time, Register Mode, PARI/O after CLK Hold Time, Buffer Mode, PARI/O after CLK Hold Time, Buffer Mode, 11A/YERREN after CLK Hold Time, Register Mode, CLKEN after CLK Pulse Width, CLK Output Skew(2) 1.7 5.9 1.2 4.6 2.4 2 2.5 0.4 0.25 0.7 0.25 0.25 0.25 0.25 0.25 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.9 5.2 1.5 3.6 2 1.9 2.6 0.25 0.25 0.4 0.25 0.25 0.25 0.25 0.5 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1.45 4.4 1.3 3.1 1.7 1.6 2.2 0.55 0.25 0.7 0.25 0.4 0.5 0.4 0.4 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 500 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps 1 3.2 -- 3.8 1.2 3.8 ns 1 6.4 -- 5.2 1.7 5 ns 1 5.6 -- 6 1 4.8 ns Min. 125 1 1 1.2 1 1 1 1 1 1.2 1.1 Max. -- 4.4 5.7 8.6 6.8 5.9 6.1 5.9 3.6 5.1 6.5 VCC = 2.7V Min. 125 -- -- -- -- -- -- -- -- -- -- Max. -- 4.2 4.9 7.9 5.2 5.8 5.5 4.9 4.2 4.9 6.4 VCC = 3.3V 0.3V Min. 125 1.1 1.4 1.7 1.3 1.3 1.2 1.2 1.9 1.5 1.4 Max. -- 3.8 4.4 6.6 4.5 4.9 4.8 4.6 4 4.2 5.4 Unit MHz ns ns ns ns ns ns ns ns ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2 Skew between any two outputs of the same package and switching in the same direction.
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IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50 6 2.7 1.5 300 300 50 VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
ALVC Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE
VCC 500 Pulse Generator
(1, 2)
VLOAD Open GND
VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
ALVC Link
VIN D.U.T. RT
VOUT
500 CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALVC Link
INPUT
tPLH1
tPHL1
VIH VT 0V VOH VT VOL VOH VT VOL
Set-up, Hold, and Release Times
OUTPUT 1
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
VT
tSK (x)
tSK (x)
OUTPUT 2 tPLH2 tPHL2
VT
ALVC Link
Pulse Width
ALVC Link
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION VCC = 2.7V AND 3.3V 0.3V
6V 500 From Output Under Test CL = 30 pF (see Note 1) 500 S1 Open GND
TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND
YERR
S1 6V 6V
Load Circuit
tPHL (see Note 8) tPLH (see Note 9)
TIMING INPUT
2.7V 1.5V 0V tW 2.7V 1.5V 1.5V 0V INPUT 1.5V 1.5V 2.7V 0V
tsu DATA INPUT
th
Voltage Waveforms Setup and Hold Times
Voltage Waveforms Pulse Duration
OUTPUT CONTROL (low-level enabling) tPZL 2.7V Input t PLH Output 1.5V 1.5V 1.5V 0V t PHL V OH 1.5V V OL OUTPUT WAVEFORM 2 S1 at GND (see Note 2) OUTPUT W AVEFORM 1 S1 at 6V (see Note 2)
1.5V 2.7V 1.5V 0V tPLZ 3V 1.5V tPZH 1.5V VOL+0.3V VOL tPHZ VOH VOH-0.3V 0V
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and DisableTimes
NOTES: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tr 2 ns, tf 2 ns. 4. The outputs are measured one at a time with one transition per measurement. 5. tPLZ and tPHZ are the same as tdis. 6. tPZL and tPZH are the same as ten. 7. tPLH and tPHL are the same as tpd. 8. tPHL is measured at 1.5V. 9. tPLH is measured at VOL +0.3V.
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IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
LOAD CIRCUIT AND VOLTAGE WAVEFORMS VCC = 2.7V AND 3.3V 0.3V
2.7V 1.5V INPUT tPLH OUTPUT t PHL 1.5V 1.5V V OL 1.5V 0V V OH
PARI/O Load Circuit
From Output Under Test PARI/O
Test Point
PARI/O of second ALVCH16903 ZO = 52 Td = 63 ps
CL = 0.6 pF (see Note 1)
CL = 0.6 pF (see Note 1)
NOTE: 1. CL includes probe and jig capacitance.
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IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION VCC = 2.5V 0.2V
2 x VCC 500 From Output Under Test CL = 30 pF (see Note 1) 500 S1 Open GND
TEST tpd tPLZ/tPZL tPHZ/tPZH YERR tPHL (see Note 8) tPLH (see Note 9)
S1 Open 2 x VCC GND S1 2 x VCC 2 x VCC
Load Circuit
TIM ING INPUT
VCC VCC/2 0V tW VCC VCC/2 VCC/2 0V INPU T VCC/2 VCC/2 VCC 0V
tsu DATA INPU T
th
Voltage Waveforms Setup and Hold Times
Voltage Waveforms Pulse Duration
INPUT CONTROL (low-level enabling) V cc Input t PLH Output V cc /2 V cc /2 V cc /2 0V tPHL VOH V cc /2 V OL OUTPUT W AVEFORM 1 S1 at 2xVcc (see Note 2) OU TPUT W AVEFOR M 2 S1 at GND (see Note 2) tPZL
V CC /2 V CC /2
VCC 0V tPLZ VCC Vcc/2 VOL+0.15V VOL tPHZ VOH VOH-0.15V 0V
tPZH Vcc/2
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and DisableTimes
NOTES: 1. CL includes probe and jig capacitance. 2. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 3. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tr 2 ns, tf 2 ns. 4. The outputs are measured one at a time with one transition per measurement. 5. tPLZ and tPHZ are the same as tdis. 6. tPZL and tPZH are the same as ten. 7. tPLH and tPHL are the same as tpd. 8. tPHL is measured at VCC /2. 9. tPLH is measured at VOL + 0.15V.
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IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
PARAMETER MEASUREMENT INFORMATION VCC = 2.5V 0.2V
From Output Under Test PARI/O
Test Point
PARI/O of second ALVCH16903 ZO = 52 Td = 63 ps
CL = 0.6 pF (see Note 1)
CL = 0.6 pF (see Note 1)
Load Circuit
V cc Input t PLH Output V cc /2 V cc /2 V cc /2 0V t PH L V OH V cc /2 V OL
Voltage Waveforms Propagation Delay Times
NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Zo = 50, tr 2 ns, tf 2ns. 3. tPLH and tPHL are the same as tpd.
RL = 10 From Output Under Test Test Point CL = 30 pF (see Note 1) Output Input t PLH V cc /2 V cc /2
V cc V cc /2 0V t PH L V OH V cc /2 V OL
Load Circuit
Voltage Waveforms Propagation Delay Times
NOTES: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Zo = 50, tr 2 ns, tf 2ns.
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IDT74ALVCH16903 3.3V CMOS 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT ALVC X XX Bus-Hold Temp. Range XXX Family XXX XX Device Type Package
PV PA PF 903 16 H 74
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package 12-Bit Universal Bus Driver with Parity Checker Double-Density, 24mA Bus-Hold -40C to +85C
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